`timescale 1ns/1ps

module sim_ivl;

  reg rst_n;
  reg clk;

  parameter CLK_PERIOD = 10;

  licore_tb tb_top (
    .clk(clk),
    .rst_n(rst_n)
  );

  initial begin
    clk = 1'b0;
    do_reset(3);
  end

  always #(CLK_PERIOD/2) clk = ~clk;

  task do_reset;
    input integer wait_cycles;
    begin
      rst_n = 1'b0;
      repeat (wait_cycles) begin
        @(posedge clk) #1;
      end
      rst_n = 1'b1;
    end
  endtask

  initial begin
    $dumpfile("sim.wave");
    $dumpvars(0, tb_top);
  end

endmodule

